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  MCZ5207SG shindengen electric mfg.co.,ltd - 1 - cat.no. 1h0 1 00 - 1 e mcz520 7sg application note jan . 201 3 ver 1.0 llc current resonant bridge controller mcz 5207 sg + + vo 1
MCZ5207SG shindengen electric mfg.co.,ltd - 2 - cautions for use thank you for purchasing our products. this manual contains important information on the safe use of our products. your safety is of the utmost importance to us. please read these instructions carefully before using our products. the following symbols mean: ! warning improper use of the products can result in death, serious injury, or expe nsive damage to equipment. ! caution improper use of the products can result in minor injuries or damage to equipment. ! ! warning warning although we are co nstantly making every effort to improve the quality and reliability of our products, there nevertheless remains a certain probability that the semiconductor products may occasionally fail or malfunction. please take careful precautions against product fail ures or malfunctions to avoid any injuries, fire accidents or social loss by implementing safety designs such as redundancy designs, designs for fire spread prevention, and designs for preventing malfunctions. our semiconductor products listed in this do cument are not designed or manufactured to be used in devices or systems requiring extremely high levels of quality and reliability, or the failure or malfunction of which may directly threaten human lives or cause injury. in the cases where the products a re to be used in devices or systems for special applications or devices or systems for specialized applications shown below, always make sure to consult us in advance. special applications transportation devices (automotive, marine, etc.), communicatio n devices for core network, traffic signal devices, fire prevention/anticrime devices, various safety devices, medical devices, etc. specialized applications nuclear power control systems, aircraft and aerospace devices, submarine relay devices, and syste ms for preserving life, etc. even if it is not for a special or specialized application, when ic products are to be used for devices or systems that are desired to last for a long period under continuous operation, please make sure to consult us in advan ce. ! ! ! ! ! caution caution caution caution caution do not attempt under any conditions to repair or modify ic products by yourself. doing so could result in electric shock, device breakage, fire, and malfunction. when an abnormal condition occurs, an excessive voltage or under voltage may be generated across the output terminals of the circuit. install preventative measures (e.g. over - voltage protection, over - current protection) for the device by considering the possibility of a malfunction and/or breakage of a load in an abnormal condition. do not switch on the circuit before confirming the proper connection and polarity of input and output terminals as an erroneous connection may cause breakage of the protection device or smoke/fire. do not use the circuit beyond the rated input voltage and install a protection device on the input rail to prevent smoke/fire that may be caused from an abnormal condition. if a breakdown or other abnormal condition occurs during the use of the device, immediately stop power to the device and consult us at your earliest possible convenience. we reserve the right to make any changes to the contents of this manual without prior notice in accordance with modifications to ic products. details of specifications should be exchanged at the adoption of the ic products. all information incl uded in this manual is believed to be accurate and reliable. however, our company takes no responsibility for any injury or damage incurred when using the ic products as described in this manual. neither do we take any responsibility for i ssues arising fro m infringement of patent or other rights caused by using this manual. the provision of this manual does not guarantee the right to use any third party?s patent or other rights, or grant permission to use the patent or other rights of our company. no part of this manual may be reproduced or copied without the specific written consent of shindengen electric mfg. co., ltd. we are happy to provide circuit design support for safe use of the ic. please consult our sales representative . index MCZ5207SG a pplication note
MCZ5207SG shindengen electric mfg.co.,ltd - 3 - 1 : g eneral description 1.1 : features 4 1.2 : internal b lock diagram 5 1.3 : pin assignment 6 1.4 : functions 6 1.5 : typical circuit configuration 7 2 : functional description 2.1: operation mode 8 2.2: supply block 8 2.2.1 : ic supply (vc1) 2.2.2 : gate driver supply (vc2) 2.2.3 : high side gate driver supply (vb) 2.3: functional terminal detail 9 - 1 7 2.3.1 : gate driver output (vgh / vgl) 2.3.2 : oscilator and feedback (fb) 2.3.3 : brown - out protection (vsen) 2.3.4 : current peak limiting fast ocp(cs1) 2.3.5 : fequency clamped slow olp (cs2/cso) 2.3.6 : capacitive mode protection (cs2) 2.3.7 : safe startup 2.3.8 : soft start (sst) 2.3.9 : timer delayed latching protection (sst) 2.3.10 : high side floating vdd (vb) 2.3.11 : active stdby (as) 2.3.12 : burst mode operation (as) 2.3.13 : thermal shutdown 2.4: thermal shut down protection 1 7 3 : selecting components value 3.1: brown out protection (vsen) 18 3.2: oscillator / feedback (fb) 19 3.3: soft start / delayed protection timer (sst) 2 0 3.4: ocp1/ocp2 and anti - capacitive mode protection 2 0 - 21 4 : circuit diagram 4.1: dcdc configuration example 2 2 5 : dimensions 23 5.1: sop16 (m cz5207sg)
MCZ5207SG shindengen electric mfg.co.,ltd - 4 - 1 general description mcz520 7 s g is an advanced symmetri c llc current resonant mode controller for bridge converter. bu il t - in high voltage direct gate drivers, control circuit and optimized protections allow simplified and space/cost - saving design of power supplies for : ? large screen flat panel tvs (pdp / lcd ) ? document equipment ? high power adapter ? cvcc high power led lighting ? high power standard psu ? high power audio amp 1.1 features 1. robust 600v direct gate driver. 2. optimized protections (oc p/burst/timer delayed latch/thermal) for llc converter. 3. bidirectional resonant current sensing . 4. bidirectional capacitive mode protection . 5. vcc suppl y up to 35v with 12.9v/8.7v uvlo . 6. built - in voltage regulator of 10.5v for gate driver. 7. independent uvlo for high side/low side gate drive v dd . 8. safe soft star t ing function to prevent mosfet didt stress. 9. brown out protection 10. resonant peak current stabilized frequency clamp olp . new 11. active stdby function to improve light load efficiency. new 12. less than 100mw no load consumption is possible with burst mode operation . new 13. latching protection with external signal is possible. new
MCZ5207SG shindengen electric mfg.co.,ltd - 5 - 1.2 block diagram sop16 + - vc 1 st / sp internal vref latch reset tsd vc 2 off as on timer counter x 2 times osc fixed dt vsen on / off sst latch ocp 1 ocp counter 8 times llc stop control logic burst on / off high voltage driver dropper as off fb discharge ss - reset ss st / sp counter reset vss reset latch stop s q r s soft start timer latch as mode as lin cso charge ocp 2 didt 1 level shift 1 3 4 5 6 7 8 16 15 14 13 12 9 10 11 2 vc 2 st / sp charge / discharge on / off fig 1 . mc z 520 7sg internal block diagram
MCZ5207SG shindengen electric mfg.co.,ltd - 6 - 1.3 pin assignment 1.4 functions pin number symbol description 1 vc1 ic supply voltage vcc input up to 35v uvlo(on) = 12. 9v / uvlo(off) = 8.7v . 2 vsen bus v oltage sen sing input for brown - out protection and on/off with external signal 3 sst s oft s tart and t imer delayed latching protection timing capacitor connecting terminal latching protection with external signal is supp orted. 4 as a ctive s tdby / burst operation signal input 5 fb f eed b ack signal input / timing capacitor and resistor connecting terminal f(min) / f(ss) / initial dead time is determined 6 cso frequency clamp c urrent s ensing comparator o utput a veraged o lp response is determined . 7 cs1 c urrent s ensing input for shorted load protection peak current limiting sensing threshold voltage is +/ - 0 . 5v. 8 cs2 c urrent s ensing input for frequency clamp and capacitive mode protection protection point can be adjuste d independently of cs1. +/ - 0.5v threshold for frequency clamp and +/ - 0.1 v for anti capacitive mode protection. 9 gnd ic g round terminal 10 vc2 stabilized vdd output for gate drive 10. 2 v 11 vgl g ate drive output for l ow side switch 12 - 13 nc not conn ected 14 vb b ootstrapped floating vdd input for h igh side gate driver 15 vs floating driver reference voltage (= source terminal of high side switch) 16 vgh g ate drive output for h igh side switch 1 . vc 1 2 . vsen 3 . sst 4 . as 5 . fb 6 . cso 7 . cs 1 8 . cs 2 9 . gnd 10 . vc 2 11 . vgl 12 . nc 13 . nc 14 . vb 15 . vs 16 . vgh fig 2 . mcz520 7 s g pin assignment
MCZ5207SG shindengen electric mfg.co.,ltd - 7 - 1.5 applicable circuit configuration most simple se pp(single ended push - pull) input ripple current reduction (half bridge) for high power application (full bridge)
MCZ5207SG shindengen electric mfg.co.,ltd - 8 - 2 functional description 2.1 operation mode mcz520 7 s g operation timing chart is shown in 2.2 and 2.3 . method of selecting components value is described in article 3 . MCZ5207SG has three operation mode : 1) normal operation mode 2) active stdby mode 3) burst operation mode normal operation is assumed in this document unless otherwise specified. active stdby mode and burst mode operation details are described in 2.3.11 and 2.3.12 . 2.2 supply voltage 2.2.1 ic main supply (vc1) vc1 uvlo threshold is 12.9v ( start ) and 8.7v ( stop ). when vc1 terminal volt age reaches to vc1(start) 12. 9 v , vc2 output is enabled and ic operation starts. when vc1 terminal voltage decreases to less than vc1(stop) 8.7 v , vc2 output is disabled and ic operation stops. latching protection is initialized when vc1 terminal voltage dec reases to less than vc1(latch reset) 8. 3 v . 2.2.2 stabilized gate drive v dd (vc2) vc2 terminal is an output of internal 10. 2 v dropper for the gate driver. v c 2 output is also a voltage source of boot strapping high side vdd. filtering capacitor should be placed close to v c 2 - gnd. please be noticed that gate driving ripple current flows in this vc2 filtering capacitor, so take care of capacitor ripple current rating. vc2 output is enabled when vc1 reaches to vc1(start) 12.9v . internal oscillator start s ope r a t ion when vc2 terminal voltage reaches to vc2(start) 9.6 v and gate drive output is enabled. refer to article 2.3 to see gate drive output timing . 2.2.3 boot strapped high side floating v dd (vb) vb is the input from vc2 voltage source through boo t strapping diode. please place boot strap filtering capacitor close to vb ? vs terminal. 600v fast and soft recovery frd like d1nk60 (axial) or d1fk60 (smd) is recommended as a boot strapping diode, snappy recovery type should n ot be chosen high side uvl o is implemented watching vb ? vs terminal voltage. vb - vs(start) is 7. 3 v and vb - vs(stop) is 5. 1 v . undesired linear operation can be prevented by this independent high side vdd uvlo.
MCZ5207SG shindengen electric mfg.co.,ltd - 9 - 2. 3 functional terminal detail 2. 3 .1 gate drive output (vg l and vgh ) gate driver output terminals are vgl (low side mosfet ) and vgh (high side mosfet ) with 0.18apk sourcing and 0.4apk sinking capability. generic gate drive connection is shown in fig.3(a). large qg gate can be handled with additional sinking diode shown in fig.3(b),(c). in this case snappy recovery diode is not recommended. soft recovery fast switching or sbd is recommended like d1ns4 (40v axial sbd) or m 1 fm3 (30v smd sbd). 2. 3 .2 osci l lator ( fb) the timing of gate drive pulse vgl and vgh is determined by charging and discharging time period of timing capacitor ct (connected between fb and gnd ) . gate output is enabled during ct discharging period . vgl and vgh are alterna tely outputted to drive each gate of mosfets. during ct charging period , both vgl and vgh are simultaneously disabled to prevent shoot through of mosfets , this time period is known as dead time ( dt ),. dt is depend on ct and rt value. please refer to electric characteristics charts fig. 3 . gate drive circuits fig. 4 . fbl ? vgl/vgh timing
MCZ5207SG shindengen electric mfg.co.,ltd - 10 - operating frequency is varied by controlling ct discharging current. ( fig.5) dead time expands according to operating frequency increase, thus zvs (zero voltage switching) operation can be easily achieved in wide input/output range and various resonant condition. minimum operating frequency ( fmin ) is determined by timing capacitor ct and timing resistor rt . ma x imum operating frequency ( fmax ) is determined by ct , rt and rfmax connected in series to fb control loop. less than 500khz is recommended in continuous operation. soft starting frequency ( fss ) is determined by ct value, fss and fmax is independent so undesired frequency increase can be avoided under heavy ccm llc operat ion. 2. 3 .3 brown - out protection (vsen) vsen terminal monitors the input bus voltag e and determines csst discharge on/off according to vse n terminal voltage. this input uvlo function prevents excessi ve resonant rush current flow and capacitive mode operation under various input brown - out condition. timing chart of vsen brown - out protection is shown in fig. 6 under input bus voltage increasing condition , csst starts to be charge d when vsen terminal v oltage reaches to vsen1(ss - reset) 3.55v and gate output is enabled when sst terminal voltage reaches to vss(st) 0.6v . operating frequency decreases according to sst terminal voltage increase s . and under input bus voltage decreasing condition, csst starts to be discharged when vsen terminal voltage decreases to vsen2(ss - reset) 3.25v . operating frequency increases gradually according to sst terminal voltage decreases and gate output is disabled when sst terminal voltage reaches to less than vss(sp) 0.5v . vs en brownout threshold voltage is switched automatically according to as terminal voltage status . n ormal operation ( as off ) : vsen on 3.5 5 v / vsen off 3.2 5 v as operation mode ( as on ) : vsen on 1.0v / vsen off 0.9v b urst operation mode : vsen on 1.0v / vsen off 0.9v freq uency vs d uty 20 25 30 35 40 45 50 55 60 0 100 200 300 400 500 600 f requency [k h z] d u t y [ % ] fb=2200pf fb=1800pf fb=1500pf fb=1000pf fb=820pf fb=470pf f requency vs dt 200 300 400 500 600 700 0 100 200 300 400 500 600 f requency [k hz] d t [ n s ] fb=2200pf fb=1800pf fb=1500pf fb=1000pf fb=820pf fb=470pf fig. 5 . gate output d uty/dead time vs frequency vsen vc 1 fb vgh sst vgl as 12 . 9 v 0 . 6 v 3 . 5 v 3 . 2 v 0 . 5 v 0 . 9 v 1 . 0 v 0 . 6 v 0 . 5 v fig. 6 . brown - out protection timing
MCZ5207SG shindengen electric mfg.co.,ltd - 11 - 2. 3 . 4 dynamic peak current limiting ocp (cs 1 ) shorted load protection ( ocp1 , hereinafter) is a fast response cycle by cycle peak current limiter . when cs1 terminal vo ltage reached to cs1 th re shold ( +/ - 0.5v ), gate drive output is disabled instantaneously and ct and also csst starts to be charged . 0.5v threshold is low enough so sensing loss is not high even when using current sensing resistor method. fig. 7 shows th e timing charts of ocp1 operation and csst charging detail is described in article 2. 3 .8 . leb is enabled during fb (top) 4.65v to 4.4v time period. so even heavy non - zvs surge current cannot trigger ocp1 . from ocp1 detection to ct charging has 200nsec time delay due to internal filter. 2.3. 5 frequency clamped averaging olp (cs2 and cso ) the MCZ5207SG has frequency clamped over load protection ( ocp2 , hereinafter). when cs2 terminal voltage reaches to +/ - 0.5v , cso starts to be charged and operating frequency increases according to cso terminal voltage increases. operating frequency and cso terminal voltage is shown in fig. 8 please be noticed that ocp2 operating point is independent from ocp1 , so de sired operating point can be adjusted. ocp internal filter delay cs 1 0 v + 0 . 5 v vgh vgl fbl ( bottom ) fbl ( top ) - 0 . 5 v blanking threshold voltage 4 . 4 v ocp blanking period fig. 7 ocp1 operation timing fig. 8 operati ng frequency vs cso terminal voltage fig. 9 cso terminal
MCZ5207SG shindengen electric mfg.co.,ltd - 12 - 2.3.6 anti - capacitive mode protection ( cs 2 ) the mcz520 7sg adopts anti - capacitive mode protection to prevent damgerous mosfet body diode di/d t operation. when cs2 terminal voltage crosses vdi/dt( +/ - ) +/ - 0. 1 v before expected gate turn off , gate output is instantaneously disabled. ( shown in fig. 1 0 ) during high side mosfet on period, high side gate turns off and ct starts charged immediately whe n cs2 terminal voltage reaches to +0.1v in negative direction.and during low side mosfet on period, low side gate turns off and ct starts to be charged when cs2 turminal voltage reaches to - 0.1v in possitive direction. to prevent malfunction caused by sw itching surge voltage , capacitive mode protection is disabled during vfb > vfb(msk) 4.4v . even i f cs2 terminal voltage crosses this threshold during this time period , anti - capacitive mode protection does not work. timer delayed latching protection i s enabled only when llc is operating in as mode. - normal and burst mode : csst will not be charged in anti - capacitive mode protection - as mode : csst will be charged during anti - capacitive mode protection operates. this anti - capacitive mode protection results in llc operating always in above zvs region, so feedback - control turnaround never occurs. 2. 3 . 7 safe - startup p rotection (tss(3)) the MCZ5207SG has another di/dt protection at startup period to prevent too fast turn - off before body diode conduction period ends. on 2 nd vgl output period, vfb (bottom) threshold voltage is switched to lower value and results in incre ase of on time period . t iming chart is shown in fig.1 1 . delay time + 0 . 06 v vgh vgl fb ( bottom ) fb ( top ) - 0 . 06 v 4 . 4 v csl 0 v blanking period fig. 1 0 . anti - capacitive mode protection timing
MCZ5207SG shindengen electric mfg.co.,ltd - 13 - 2.3.8 soft start (sst) during starting period , operating frequency decreases from soft start frequency ( fss ) to stabiliz e d frequency proportionally to sst terminal voltage to prevent excessive resonant current or output inrush current and capacitive mode operation. csst starts to be charged under two conditions as below : 1. vc1 > vc1(start) 12.9v and 2. vsen terminal voltag e > vsen1(ss - reset) or vsen3(ss - reset) oscillator starts operation at vsst = 0.6v and operating frequency is stabilized before vss t reaches to vss(open) 2.1v . fig.1 2 shows frequency and vsst characteristics . 2. 3 . 9 timer delayed latching protection (sst) csst also functions as latching protection timing capacitor. sst terminal capacitor csst starts to be charged in two condition as following: 1. o cp 1 or ocp2 operates continuously or 2. anti - c apac itive mode protection operates in as mode. when csst is charged continuously and sst terminal voltage reaches to vtimer(set) 3. 5 v , long interval intermittent protection starts. after specified time period, normal operati on restarts when abnormal condi ti on was removed. if abnormal condition has not been removed, ic enters into latched off mode after second intermittent operation finished . vgh vgl v fb ( bottom ) v fb ( top ) vth ( tss 3 ) idh idl fig. 1 1 tss(3) operati on timing chart v s s t vs fre qu e n c y 0 50 100 150 200 250 300 350 400 450 500 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 v s s t [ v ] f r e q u e n c y [ k h z ] ct=1500pf ct=1200pf ct=1000pf ct=820pf fig. 1 2 operation frequency and sst term inal voltage 1 st bootstrap charging current
MCZ5207SG shindengen electric mfg.co.,ltd - 14 - to initialize latching status, restart vc1 to vc1<8 . 3 v . protection timing chart is shown in fig. 1 3 . csst charging c urrent is depend on cso terminal voltage during continuous ocp2 operat ion . table 1. csst charging current protection status csst charging current ocp1 40ua ocp2 1.0v < vcso < 1.75v 1.9ua vcso 1.75v 40ua anti - capacitive (during as mode) 40ua int ern al latching counter is initiali zed in two conditions as following: 1) vsst decreases to 2.1v ( recovered to normal operation ) 2) csst discharging condition ( vc1 on/off , vsen on/off ) l atching counter initialization helps to avoid undesirable latching. when abnormal condition is counted twice, ic enters in to latched stop mode. 2. 3 . 10 boot strapping circuit high side floating vdd ( vb - vs ) capacitor is charge d during condu ction peri od of low side mosfet as shown in fig. 14 . vb ? vs voltage is simply equals to ( vc 2 ? vf of dboot ) . although very stable operation is possible due to stabilized vc2 voltage, if huge negative surge voltage superimposed to vb , please add zen e r diod e clamp of 15v to avoid high side logic malfunction. this surge voltage is caused by parasitic inductance in main switching loop and huge turn off current . sst mosfet idrain abnormal status signal ( ic internal vtimer 1 2 . 1 v vtimer 2 shorted load condition short time over load vc 1 vc 1 ( stop ) 8 . 7 v vc 1 ( start ) 12 . 9 v ocp operates 0 . 35 v 3 . 5 v 0 . 6 v 1 . 5 v ocp operates ocp operates fig. 1 3 csst timing chart
MCZ5207SG shindengen electric mfg.co.,ltd - 15 - np dboot cboot 0 . 1 uf 16 v d 1 nk 60 d 1 fk 60 vc 2 pgnd mcz 5207 sg vb vs vgh vgl fig. 14 boot strap ping circuit
MCZ5207SG shindengen electric mfg.co.,ltd - 16 - 2.3.1 1 active stdby asymm etric operation (as) the MCZ5207SG has asymmetric operation mode called active standby mode to improve light load efficiency. when as terminal voltage less than vas(on) 0.8v , operation enters into asymmetric operation mode. after entering in as mode, ope ration will return to normal symmetric operation mode when as terminal voltage reaches to more than vas(off) 1.0v . to avoid undesirable as mode operation, add 1nf ? 10nf closed to as terminal. (even when as function is not used, add filtering capacitor .) as terminal open voltage is 2.5v. circuit configuration is shown in fig. 15 . when as signal is not applied ( vas(open) 2.5v ), vgh and vgl output is symmetrically 50% duty cycle, and if as terminal is pulled down externally to less than 2.2v, ct charging threshold of low side mosfet starts decreasing. this threshold decreasing is proportional to as terminal voltage and finally reaches to bottom value of threshold when as terminal voltage re aches to 1.0v. decreasing of ct discharging thre shold results in vgl pulse width increasing . maximum duty unbalance is 1:2 ( vgh : vgl ). when operation is switched to as mode, - vsen threshold ( ss - reset) is switched from 3.5 5 v/3.2 5 v to 1.0v/0.9v . - csst charging enabled if anti - capacitive protection operat es. fig. 15 as signal configuration example fig. 16 asymmetric gate output example
MCZ5207SG shindengen electric mfg.co.,ltd - 17 - 2.3.12 burst mode operation (as) burst mode operation starts when more than 4.5v external voltage is applied to as terminal. csst is discharged to 0.5v that results in gate output disabled. and when as terminal voltage decreases to 4.0v , csst starts to be charged and starting cycle begins. during burst mode operation, csst charging current is switched from 30ua to 60ua to shorten starting time period. also vsen threshold voltage is switched to 1.0v(on) / 0.9v(off) preparing to pfc stop ped llc operation. operation will recover to normal continuous operation when as terminal voltage decreases to 3.0v or less. fig. 18 burst w/external signal configuration exa mple 2.4 thermal shut down protection (tsd) the MCZ5207SG implements thermal shut down protection. threshold temperature is tsd 140 ? c mi n. with 40 ? c hysteresis . during tsd mode, ic operation entirely stops. burst signal v output vsst vsen hi lo vgl / vgh operation mode symmetric vas 4 . 5 v 4 . 0 v 3 . 0 v 2 . 1 v symmetric asymmetric asymmetric symmetric 0 v 0 . 6 v 0 . 5 v vsen threshold 3 . 5 / 3 . 2 v 3 . 5 / 3 . 2 v 1 . 0 / 0 . 9 v 1 . 0 / 0 . 9 v 3 . 5 / 3 . 2 v sst charge up vo ( reg ) fig. 17 burst mode operation timing
MCZ5207SG shindengen electric mfg.co.,ltd - 18 - 3 selecting components value 3.1 input brown out protection (vsen) vsen ss reset threshold voltage is 3.55v/3.25v . ( as mode off) 1.0v/0.9v . ( as mode on) vsen terminal sink current is less than 0.2ua ,so 20ua or more sensing bias current is recommended not to be affected by the sink current. con nect a capacitor of 1000 to 10000pf bet ween vsen and gnd for filtering . low side resistor, rvsensel(init) is obtained from formula (1) . correct value of vbulkreset threshold is obtained from formula (2) using actual value of rvsensel . in as mode operatio n, use formula (3) . ??? 1 ??? 2 ??? 3 fig. 19 vsen internal block r v s e n s e h r v s e n s e l ss reset + - vbulk input vc 1 uvlo vc 1 & vc 2 internal vref 5 v 1 0 0 0 p f ~ 1 0 0 0 0 p f as off 3 . 55 v / 3 . 25 v as on burst on 1 . 0 v / 0 . 9 v as pin low : as on 9 . 0 r r r v 3.25 r r r v 3.25 - v r 3.25 r vsensel vsensel vsenseh on) (as bulkreset vsensel vsensel vsenseh bulkreset bulkreset vsenseh (init) vsencel ? ? ? ? ? ? ? ?
MCZ5207SG shindengen electric mfg.co.,ltd - 19 - 3.2 oscillator / feedback ( fb ) operating frequency can be controlled by pulling current from fb terminal. ct , rt and rf b connected to fb terminal determin e minimum frequency ( fmin ),maximum frequency ( fmax ) , starting frequency ( fss ) and dead time ( dt ). 3. 2 .1 dead time and soft start frequency (ct ) dead time and soft start frequency fss are determined by ct capacitance. select ct capacitance from chara cteristic specification sheet. capacitance value of ct of 47 0pf to 2200pf is recommended due to the relation with dead time . 3. 2 .2 minimum frequency fmin (rt resistance) minimum frequency fmin is determined by rt value . ( connect between fb and gnd .) r elation between rt resistance and frequency is shown in characteristic specification sheet. the estimated value of fmin is obtained from formula ( 4 ) to ( 6 ). tcharge is a dead time and tdischarge is on time period of vgl / vgh . calculated value is an estima ted value including small error due to comparator delay time of around 100nsec. ( vfbl(bottom) : 3.5 v , vfbl(top) : 4.65 v ) 3. 2 .3 maximum frequency fmax (fb resi stor ) maximum frequency fmax is determined rt and rfb value . c heck the characteristic specification sheet and determine the maximum frequency . ) ( 3 ) ( ) ( 3 ) ( arg 10 0 . 7 10 0 . 7 bottom bottom top top e ch vfb rt vfb ct rt vfb rt vfb ct rt t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ---- ( 4 ) ) ( ) ( arg ln top bottom e disch vfb vfb ct rt t ? ? ? ? ---- ( 5 ) ? ? e disch e ch t t f arg arg min 2 1 ? ? ? ---- ( 6 )
MCZ5207SG shindengen electric mfg.co.,ltd - 20 - 3.3 soft start / timer delayed protection (sst) soft start charging current iss(charge) is 30 ua . whe n sst voltage rises to 0.6 v , gate output starts and timer charging is enabled when sst voltage rises to 1.5v . soft start ing time tss is a time period in which sst voltage rises from 0.6v to 1.5v . tss is obtained from formula ( 7 ) . operating frequency and ??? ( 7 ) timer charging current itimer(charge)1 is 40ua and output disable threshold voltage is 3. 5 v . thus, timer charging time ttimer is obtained from formula (8) . ??? ( 8 ) timer charging current is different w hen ocp2 is operating. if cso terminal voltage is less than 1.75v , charging current itimer(charge)2 is 1.9ua ,so time period to operation stop ( v sst =3.5v ) ttimer is obtained from formula (9) . ??? (9) if cso terminal voltage is grater t han 1.75v , charging current itimer(charge)3 = 40ua ,so time period to operation stoop ttimer is obtained from formula (8) . csst discharging current itimer(discharge) is 6 . 5 ua and operation restarts when sst terminal voltage decreases to less than vtimer(r eset) 0.35v . so gate output disabling time period is obtained from formula (10) . ??? ( 1 0 ) 3.4 ocp1/ocp2 and anti - capacitive mode protection ( cs 1 / cs2 ) current sensing connection example is shown in fig. 20 t ype (a) is cs1/2 independent sensing and (b) shows cs1/2 comm o n sensing connection. generally ocp2 operating point is lower than ocp1 ? s . in this condition ocp2 stabilize s llc operating frequency in transient over load / peak load condition and ocp1 finally halts entire llc operation in shorted load condition. current sensing resistor rocpdet is calculated from desired ocp threshold ipk using f ormula ( 11 ) . when the connection is assumed as type(a) , t entative value of rocpl(init) is obtained from formula( 12 ) and correct value of resonant current peak ipk(act) is calculated from formula( 13 ) using actual value of rocpl . considering cs1/2 terminal sourcing current 95ua, 10 ? 47 ohm is recommended for rocph . cs2 terminal sensing voltage is also used for ant - capacitive mode protection. cs2 operating point should be determined considering +/ - 0.10 v ca p acitive mode prot ection threshold. conne ct filtering capacitor of 1nf to 10nf close to cs1 or cs2 terminal to suppress ocp malfunction. frequency stabilized olp (ocp2) realizes smooth constant power output characteristics and resonant current envelope, they are very suita ble for audio amp or huge peak current flowing application. a ctual example of output characteristics is shown in fig.21. please be noticed that setting cs2 operating point to too high level causes undesirable anti - capacitive mode protecting operation in n ormal load condition. 6 10 30 9 . 0 ? ? ? ? ss ss c t 6 10 40 4 . 1 ? ? ? ? ss timer c t 6 ) ( 10 5 . 6 15 . 3 ? ? ? ? ss dis timer c t 6 10 9 . 1 4 . 1 ? ? ? ? ss timer c t
MCZ5207SG shindengen electric mfg.co.,ltd - 21 - output v/i characteristics v o u t i out fig. 21 olp characteristics example c r c r (a) cs1/2 independent sensing (b) cs1/2 common sensing fig. 20 cs1 and cs2 current sensing circuit ) 13 ( ] [ ) 12 ( ] [ ) 11 ( ] [ det ) 2 / 1 ( ) 2 / 1 ( ) 2 / 1 ( ) ( det ) 2 / 1 ( ) 2 / 1 ( ) det( ??? ??? ??? a 0.5 r r r r i ohm 0.5 r ipk r 0.5 r ohm ipk 0.5 r ocp ocpl ocpl ocph act pk ocp ocph ocpl init ocp ? ? ? ? ? ? ? ? ?
MCZ5207SG shindengen electric mfg.co.,ltd - 22 - 4 circuit diagram 4.1 configuration example of dc to dc dual output llc
MCZ5207SG shindengen electric mfg.co.,ltd - 23 - 5 dimension 5.1 sop 16 (mcz520 7sg )
MCZ5207SG shindengen electric mfg.co.,ltd - 24 - notes:


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